1. Field of the Invention
This application relates to semiconductor memory devices, and more particularly, to multi-voltage generators generating a program voltage, a read voltage and a high voltage in response to the operating mode of flash memory devices.
2. Description of the Related Art
With the development of mobile information terminals such as cellular phones using digital information communication networks such as the Internet, nonvolatile memory devices are in the spotlight as memory devices capable of storing information of the mobile information terminals in a nonvolatile manner. The nonvolatile memory device includes a flash memory that can electrically erase a predetermined number of bits of data stored therein and electrically record data.
The flash memory includes several sectors, each having several memory cells. The flash memory erases (deletes) memory cell data block by block (sector by sector) and programs (records) data cell by cell. A NAND type flash memory has a level of integration and a memory capacity as high as those of a dynamic RAM and thus it has various uses. The NAND type flash memory has a structure such that a memory string, including memory cells serially connected is serially connected, between a bit line and a source line. Multiple of memory strings from a memory cell array.
FIG. 1 is a block diagram of a conventional flash memory 100. Referring to FIG. 1, the flash memory 100 includes a block memory cell array 110, a wordline decoder 120, a high voltage generator 130, a program voltage generator 140, and a read voltage generator 150. The flash memory 100 can include several block memory cell arrays 110. Each block memory cell 110 has a corresponding wordline decoder 120. Although, for convenience of explanation, only one single wordline decoder 120 corresponding to one block memory cell 110 will be explained, flash memory decoders may include multiple block memory cell arrays 110 and wordline decoders 120.
The block memory cell array 110 includes memory strings CS respectively connected to n bit lines BL0, BL1, . . . , BLn-1. The memory strings CS are commonly connected to a source line CSL. The gates of memory cells MO through M15 of the memory strings CS are respectively connected to wordlines WL0 through WL15. The gates of string select transistors SST, connecting the memory strings CS to the bit lines BL0, BL1, . . . , BLn-1, are connected to a string select line SSL. The gates of ground select transistors GST connecting the memory strings CS to the common source line CSL, are connected to a ground select line GSL.
The wordline decoder 120 selectively activates the string select line SSL, the ground select line GSL, and wordlines WL0 through WL15 of the memory cell array 110. The wordline decoder 120 includes a decoding unit 122 receiving address signals ADDR to generate wordline driving signals S0 through S15, a string select voltage VSSL, a ground select voltage VGSL, and a wordline driver 124 transmitting the wordline driving signals S0 through S15, the string select voltage VSSL and the ground select voltage VGSL to the wordlines WL0 through WL15, the string select line SSL and the ground select line GSL.
The decoding unit 122 decodes the received address signals ADDR and provides corresponding driving voltages to the string select line SSL, the wordlines WL0 through WL15 and the ground select line GSL in a program operation, an erase operation or a read operation. The driving voltages include a program voltage Vpgm, an erasure voltage Verase, a read voltage Vread, and a pass voltage Vpass.
The wordline driver 124 includes high-voltage pass transistors SN, WN0 through WN15, GN and CN respectively connecting the string select voltage VSSL, the wordline driving signals S0 through S15, the ground select voltage VGSL, and a common source line voltage VCSL to the string select line SSL, the wordlines WL0 through WL15, the ground select line GSL, and the common source line voltage CSL. A high voltage VPP generated by the high voltage generator 130 is provided to a block wordline BLKWL to which the gates of the high-voltage pass transistors SN, WN0 through WN15, GN and CN are connected.
The high voltage generator 130 generates the high voltage VPP according to a charge pumping operation. The high voltage VPP has a level of 22V through 25V, for example. The program voltage generator 140 generates the program voltage Vpgm according to a charge pumping operation. The program voltage Vpgm is increased with the number of programming times and has a level of 15V through 20V, for example.
The read voltage generator 150 generates the read voltage Vread according to a charge pumping operation. The read voltage Vread has a level of 4.5V through 5V approximately. Each of the high voltage generator 130, the program voltage generator 140, and the read voltage generator 150 may be a simple voltage generator as shown in FIG. 2.
Referring to FIG. 2, the high voltage generator 130 may include a voltage pumping unit 210 that sequentially pumps charges when a pumping clock signal PUMP_CLK is applied thereto to generate the high voltage VPP. The high voltage VPP is provided to a voltage trimming controller 220. The voltage trimming controller 220 generates a first voltage VI divided from the high voltage VPP in response to a control signal CONTROL. A comparator 230 compares the first voltage V1 to a reference voltage Vref. When the first voltage V1 is lower than the reference voltage Vref, the comparator 230 activates the pumping clock signal PUMP_CLK. The activated pumping clock signal PUMP_CLK enables the charge pumping operation of the voltage pumping unit 210 to increase the level of the high voltage VPP. When the first voltage V1 is substantially identical to or higher than the reference voltage Vref, the comparator 230 deactivates the pumping clock signal PUMP_CLK. The deactivated pumping clock signal PUMP_CLK disables the charge pumping operation of the voltage pumping unit 210.
The control signal CONTROL is used to change the level of the high voltage VPP. Referring to FIG. 1, the high voltage VPP generated by the high voltage generator 130 is provided to the block wordline BLKWL. In a programming operation of the flash memory 100, the program voltage Vpgm is applied to a wordline connected to a memory cell to be programmed, for example, the first wordline WL0, and the pass voltage Vpass is applied to the other wordlines WL1 through WL15. To provide the program voltage Vpgm generated by the program voltage generator 140 to the first wordline WL0, the decoding unit 122 outputs the program voltage Vpgm as the wordline driving signal S0 and the high voltage VPP is applied to the block wordline BLKWL to turn on the pass transistor WN0.
Here, the program voltage Vpgm is increased with the number of programming times. The high voltage VPP has at least a level substantially equal to the threshold voltage Vth of the pass transistor WN0 plus the program voltage Vpgm such that the program voltage Vpgm is transmitted without having voltage drop. However, the high voltage VPP generated by the high voltage generator 130 has a sufficiently high level, for example, 22V through 25V, irrespective of the level of the program voltage Vpgm. The high voltage VPP having a level of 22V through 25V corresponds to a voltage obtained by adding the threshold voltages Vth of the high-voltage pass transistors SN0, WL0 through WL15, GN and CN to the maximum program voltage Vpgm.
However, the threshold voltages Vth of the pass transistors SN0, WL0 through WL15, GN and CN may vary within a semiconductor fabrication process. Accordingly, the high voltage generator 130 requires a trimming operation that controls the level of the high voltage VPP according to the control signal CONTROL.
In the programming operation, the block wordline BLKWL for transmitting the program voltage Vpgm to the wordlines WL0 through WL15 has a voltage level as high as the program voltage Vpgm plus the threshold voltages Vth of the high-voltage pass transistors SN0, WL0 through WL15, GN and CN.
However, the high voltage generator 130 generates the high voltage VPP having a sufficiently high fixed voltage level irrespective of the level of the program voltage Vpgm and transmits the high voltage VPP to the block wordline BLKWL, resulting in unnecessary power consumption. Furthermore, the high voltage generator 130 requires the trimming operation according to the control signal CONTROL when it changes the fixed high voltage level VPP.
Referring to FIG. 2, the program voltage generator 140 and the read voltage generator 150 respectively generate the program voltage Vpgm and the read voltage Vread, similar to the high voltage generator 130.